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20nm flash chip means more mobile-device features, smaller SSDs

Micron-Intel venture plans to create a 128GB SSD smaller than a postage stamp

By reducing its NAND flash chip size by as much as 40%, Intel and Micron have opened the door for tablets and smartphone manufacturers to use the extra space for product improvements such as a bigger battery, larger screen or adding another chip to handle new features.

It also means solid state drives (SSD) with twice the capacity of current drives.

This week, Intel and Micron officially announced their joint chip manufacturing venture, IM Flash Technologies (IMFT), is producing NAND flash memory with circuitry almost half the size of its current products, or 20 nanometers (nm) in width.

A size comparison between IMFT's current NAND flash chips

Micron told Computerworld about IMFT's advancement in NAND flash lithography technology earlier this month. At that time, the company said that by early summer it plans to produce a new enterprise-class solid state drive (SSD) based on the PCIe expansion card standard that won't be using the new 20nm NAND but the 34nm multi-level cell (MLC) NAND process technology. Even so, Micron said its new PCIe SSD cards will be the highest performing to date.

The new PCIe card, called the P320h, follows Micron's first enterprise-class SSD, the P300, which is based on the serial ATA (SATA) interface and single-level cell (SLC) NAND flash memory.

While the new 20nm chips have the same capacity as their 25nm predecessors, the same lithography process will also produce a single (monolithic) 16GB die, with samples available in the second half of 2011. This will effectively double the capacity for SSDs, a Micron spokeswoman said.

When the 20nm chips go into mass production later this year, Intel and Micron said they also expect to unveil samples of their 16GB chip, creating up to 128GBs of capacity in a single solid-state drive that is smaller than a U.S. postage stamp.

The new 20nm chips have the highest capacity for their form factor of any in the market today and are targeted for use in tablets, smartphones and other consumer electronic devices.

Even at 25nm, IMFT is approaching atomic sizes with its circuitry. For example, a human hair is 3,000 times thicker than 25nm.

IMFT also stated that by shrinking NAND lithography to 20nm is the most cost-effective way for increasing fabrication output, as it provides approximately 50% more gigabyte capacity from these factories when compared to current technology.

The new 20nm process maintains similar performance and endurance as the previous generation 25nm NAND technology.

Lucas Mearian covers storage, disaster recovery and business continuity, financial services infrastructure and health care IT for Computerworld. Follow Lucas on Twitter at @lucasmearian or subscribe to Lucas's RSS feed . His e-mail address is [email protected] .

Read more about storage in Computerworld's Storage Topic Center.


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