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NEC plans to break chip size barrier next year

Busting the 0.1 micron barrier could halve chip sizes

Japanese microchip manufacturer NEC Corporation is planning to build the world’s smallest processors using next-generation 0.095 micron process technology. If its plan goes ahead next summer, the Tokyo-based company will become one of the first chip makers to break the 0.1 micron barrier.

A micron is a thousandth of a millimeter, and the use of micron measurements in chip production represents the smallest gap that can exist between circuits on the surface of the chip. Current state-of-the art chips are 0.13 micron. Getting the manufacturing process below 1 micron is regarded by chip manufacturers as difficult and expensive.

The next steps in producing slimmer chips would be to go to 0.11 or 0.10 micron, and then to 0.08 micron. However, the generational jump from 0.13 micron to 0.095 micron, planned by NEC, would almost double the density of components on a chip, bringing reduced power consumption and better performance. More complex chips also enable smaller and more advanced portable electronic products.

NEC will initially use the 0.095 manufacturing process to make large scale integrated circuit (LSI) chips. LSI chips are custom designed to do a particular job, such as running a mobile phone or personal digital assistant (PDA).

Sample production is expected to begin in August, with full-scale production planned from November 2001. The new chips will be produced at NEC's wafer fabrication plant in Yamagata, the company's most advanced semiconductor production line, which was opened earlier this year.


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